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Features
* High-performance, Low-power AVR(R) 8-bit Microcontroller * RISC Architecture
- 118 Powerful Instructions - Most Single Clock Cycle Execution - 32 x 8 General Purpose Working Registers - Fully Static Operation - Up to 16 MIPS Throughput at 16 MHz Data and Non-volatile Program Memory - 2K Bytes of In-System Programmable Program Memory Flash Endurance: 10,000 Write/Erase Cycles - 128 Bytes of In-System Programmable EEPROM Endurance: 100,000 Write/Erase Cycles - 128 Bytes Internal SRAM - Programming Lock for Flash Program and EEPROM Data Security Peripheral Features - 8-bit Timer/Counter with Separate Prescaler - 8-bit High-speed Timer with Separate Prescaler 2 High Frequency PWM Outputs with Separate Output Compare Registers Non-overlapping Inverted PWM Output Pins - Universal Serial Interface with Start Condition Detector - 10-bit ADC 11 Single Ended Channels 8 Differential ADC Channels 7 Differential ADC Channel Pairs with Programmable Gain (1x, 20x) - On-chip Analog Comparator - External Interrupt - Pin Change Interrupt on 11 Pins - Programmable Watchdog Timer with Separate On-chip Oscillator Special Microcontroller Features - Low Power Idle, Noise Reduction, and Power-down Modes - Power-on Reset and Programmable Brown-out Detection - External and Internal Interrupt Sources - In-System Programmable via SPI Port - Internal Calibrated RC Oscillator I/O and Packages - 20-lead PDIP/SOIC: 16 Programmable I/O Lines - 32-lead QFN/MLF: 16 programmable I/O Lines Operating Voltages - 2.7V - 5.5V for ATtiny26L - 4.5V - 5.5V for ATtiny26 Speed Grades - 0 - 8 MHz for ATtiny26L - 0 - 16 MHz for ATtiny26 Power Consumption at 1 MHz, 3V and 25C for ATtiny26L - Active 16 MHz, 5V and 25C: Typ 15 mA - Active 1 MHz, 3V and 25C: 0.70 mA - Idle Mode 1 MHz, 3V and 25C: 0.18 mA - Power-down Mode: < 1 A
*
*
8-bit Microcontroller with 2K Bytes Flash ATtiny26 ATtiny26L Summary
*
* * * *
Not recommended for new design
1477J-AVR-06/07
Pin Configuration
PDIP/SOIC
(MOSI/DI/SDA/OC1A) PB0 (MISO/DO/OC1A) PB1 (SCK/SCL/OC1B) PB2 (OC1B) PB3 VCC GND (ADC7/XTAL1) PB4 (ADC8/XTAL2) PB5 (ADC9/INT0/T0) PB6 (ADC10/RESET) PB7 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 PA0 (ADC0) PA1 (ADC1) PA2 (ADC2) PA3 (AREF) GND AVCC PA4 (ADC3) PA5 (ADC4) PA6 (ADC5/AIN0) PA7 (ADC6/AIN1)
MLF Top View
PB2 (SCK/SCL/OC1B) PB1 (MISO/DO/OC1A) PB0 (MOSI/DI/SDA/OC1A) NC NC NC PA0 (ADC0) PA1 (ADC1) 32 31 30 29 28 27 26 25
NC (OC1B) PB3 NC VCC GND NC (ADC7/XTAL1) PB4 (ADC8/XTAL2) PB5
1 2 3 4 5 6 7 8
24 23 22 21 20 19 18 17
NC PA2 (ADC2) PA3 (AREF) GND NC NC AVCC PA4 (ADC3)
Note:
The bottom pad under the QFN/MLF package should be soldered to ground.
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ATtiny26(L)
1477J-AVR-06/07
NC (ADC9/INT0/T0) PB6 (ADC10/RESET) PB7 NC (ADC6/AIN1) PA7 (ADC5/AIN0) PA6 (ADC4) PA5 NC
9 10 11 12 13 14 15 16
ATtiny26(L)
Description
The ATtiny26(L) is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATtiny26(L) achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed. The AVR core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers. The ATtiny26(L) has a high precision ADC with up to 11 single ended channels and 8 differential channels. Seven differential channels have an optional gain of 20x. Four out of the seven differential channels, which have the optional gain, can be used at the same time. The ATtiny26(L) also has a high frequency 8-bit PWM module with two independent outputs. Two of the PWM outputs have inverted non-overlapping output pins ideal for synchronous rectification. The Universal Serial Interface of the ATtiny26(L) allows efficient software implementation of TWI (Two-wire Serial Interface) or SM-bus interface. These features allow for highly integrated battery charger and lighting ballast applications, low-end thermostats, and firedetectors, among other applications. The ATtiny26(L) provides 2K bytes of Flash, 128 bytes EEPROM, 128 bytes SRAM, up to 16 general purpose I/O lines, 32 general purpose working registers, two 8-bit Timer/Counters, one with PWM outputs, internal and external Oscillators, internal and external interrupts, programmable Watchdog Timer, 11-channel, 10-bit Analog to Digital Converter with two differential voltage input gain stages, and four software selectable power saving modes. The Idle mode stops the CPU while allowing the Timer/Counters and interrupt system to continue functioning. The ATtiny26(L) also has a dedicated ADC Noise Reduction mode for reducing the noise in ADC conversion. In this sleep mode, only the ADC is functioning. The Power-down mode saves the register contents but freezes the oscillators, disabling all other chip functions until the next interrupt or hardware reset. The Standby mode is the same as the Power-down mode, but external oscillators are enabled. The wakeup or interrupt on pin change features enable the ATtiny26(L) to be highly responsive to external events, still featuring the lowest power consumption while in the Power-down mode. The device is manufactured using Atmel's high density non-volatile memory technology. By combining an enhanced RISC 8-bit CPU with Flash on a monolithic chip, the ATtiny26(L) is a powerful microcontroller that provides a highly flexible and cost effective solution to many embedded control applications. The ATtiny26(L) AVR is supported with a full suite of program and system development tools including: Macro assemblers, program debugger/simulators, In-circuit emulators, and evaluation kits.
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1477J-AVR-06/07
Block Diagram
Figure 1. The ATtiny26(L) Block Diagram
VCC 8-BIT DATA BUS INTERNAL OSCILLATOR GND
PROGRAM COUNTER STACK POINTER
INTERNAL CALIBRATED OSCILLATOR
WATCHDOG TIMER MCU CONTROL REGISTER
TIMING AND CONTROL
PROGRAM FLASH
SRAM
AVCC
INSTRUCTION REGISTER GENERAL PURPOSE REGISTERS
X Y Z
MCU STATUS REGISTER TIMER/ COUNTER0 TIMER/ COUNTER1
INSTRUCTION DECODER
CONTROL LINES
ALU
UNIVERSAL SERIAL INTERFACE
STATUS REGISTER
INTERRUPT UNIT
PROGRAMMING LOGIC
ISP INTERFACE
EEPROM
OSCILLATORS
ANALOG COMPARATOR
DATA REGISTER PORT A
DATA DIR. REG.PORT A
ADC
DATA REGISTER PORT B
DATA DIR. REG.PORT B
+ -
PORT A DRIVERS
PORT B DRIVERS
PA0-PA7
PB0-PB7
4
ATtiny26(L)
1477J-AVR-06/07
ATtiny26(L)
Pin Descriptions
VCC GND AVCC Digital supply voltage pin. Digital ground pin. AVCC is the supply voltage pin for Port A and the A/D Converter (ADC). It should be externally connected to VCC, even if the ADC is not used. If the ADC is used, it should be connected to VCC through a low-pass filter. See page 96 for details on operating of the ADC. Port A is an 8-bit general purpose I/O port. PA7..PA0 are all I/O pins that can provide internal pull-ups (selected for each bit). Port A has alternate functions as analog inputs for the ADC and analog comparator and pin change interrupt as described in "Alternate Port Functions" on page 48. Port B is an 8-bit general purpose I/O port. PB6..0 are all I/O pins that can provide internal pull-ups (selected for each bit). PB7 is an I/O pin if not used as the reset. To use pin PB7 as an I/O pin, instead of RESET pin, program ("0") RSTDISBL Fuse. Port B has alternate functions for the ADC, clocking, timer counters, USI, SPI programming, and pin change interrupt as described in "Alternate Port Functions" on page 48. An External Reset is generated by a low level on the PB7/RESET pin. Reset pulses longer than 50 ns will generate a reset, even if the clock is not running. Shorter pulses are not guaranteed to generate a reset. XTAL1 XTAL2 Input to the inverting oscillator amplifier and input to the internal clock operating circuit. Output from the inverting oscillator amplifier.
Port A (PA7..PA0)
Port B (PB7..PB0)
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1477J-AVR-06/07
Resources
A comprehensive set of development tools, application notes and datasheets are available for download on http://www.atmel.com/avr.
6
ATtiny26(L)
1477J-AVR-06/07
ATtiny26(L)
About Code Examples
This datasheet contains simple code examples that briefly show how to use various parts of the device. These code examples assume that the part specific header file is included before compilation. Be aware that not all C compiler vendors include bit definitions in the header files and interrupt handling in C is compiler dependent. Please confirm with the C compiler documentation for more details.
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1477J-AVR-06/07
Register Summary
Address
$3F ($5F) $3E ($5E) $3D ($5D) $3C ($5C) $3B ($5B) $3A ($5A) $39 ($59) $38 ($58) $37 ($57) $36 ($56) $35 ($55) $34 ($54) $33 ($53) $32 ($52) $31 ($51) $30 ($50) $2F ($4F) $2E ($4E) $2D ($4D) $2C ($4C) $2B ($4B) $2A ($4A) $29 ($49) $28 ($48) $27 ($47) $26 ($46) $25 ($45) $24 ($44) $23 ($43) $22 ($42) $21 ($41) $20 ($40) $1F ($3F) $1E ($3E) $1D ($3D) $1C ($3C) $1B ($3B) $1A ($3A) $19 ($39) $18 ($38) $17 ($37) $16 ($36) $15 ($35) $14 ($34) $13 ($33) $12 ($32) $11 ($31) $10 ($30) $0F ($2F) $0E ($2E) $0D ($2D) $0C ($2C) $0B ($2)B $0A ($2A) $09 ($29) $08 ($28) $07 ($27) $06 ($26) $05 ($25) $04 ($24) ... $00 ($20)
Name
SREG Reserved SP Reserved GIMSK GIFR TIMSK TIFR Reserved Reserved MCUCR MCUSR TCCR0 TCNT0 OSCCAL TCCR1A TCCR1B TCNT1 OCR1A OCR1B OCR1C Reserved PLLCSR Reserved Reserved Reserved Reserved Reserved Reserved Reserved WDTCR Reserved Reserved EEAR EEDR EECR PORTA DDRA PINA PORTB DDRB PINB Reserved Reserved Reserved Reserved Reserved Reserved USIDR USISR USICR Reserved Reserved Reserved Reserved ACSR ADMUX ADCSR ADCH ADCL Reserved Reserved
Bit 7
I SP7 -
Bit 6
T SP6 INT0 INTF0 OCIE1A OCF1A
Bit 5
H SP5 PCIE1 PCIF OCIE1B OCF1B
Bit 4
S SP4 PCIE0 -
Bit 3
V SP3 -
Bit 2
N SP2 TOIE1 TOV1
Bit 1
Z SP1 TOIE0 TOV0
Bit 0
C SP0 -
Page
11 12 60 61 61 62
-
PUD -
SE -
SM1 -
SM0 WDRF PSR0
BORF CS02
ISC01 EXTRF CS01
ISC00 PORF CS00
38 37 68 69 30
Timer/Counter0 (8-Bit) Oscillator Calibration Register COM1A1 CTC1 COM1A0 PSR1 COM1B1 COM1B0 FOC1A CS13 FOC1B CS12 PWM1A CS11 PWM1B CS10
72 73 74 74 75 75
Timer/Counter1 (8-Bit) Timer/Counter1 Output Compare Register A (8-Bit) Timer/Counter1 Output Compare Register B (8-Bit) Timer/Counter1 Output Compare Register C (8-Bit) PCKE PLLE PLOCK
-
-
-
WDCE
WDE
WDP2
WDP1
WDP0
80
PORTA7 DDA7 PINA7 PORTB7 DDB7 PINB7
EEAR6 PORTA6 DDA6 PINA6 PORTB6 DDB6 PINB6
EEAR5 PORTA5 DDA5 PINA5 PORTB5 DDB5 PINB5
EEAR4 PORTA4 DDA4 PINA4 PORTB4 DDB4 PINB4
EEAR3 EERIE PORTA3 DDA3 PINA3 PORTB3 DDB3 PINB3
EEAR2 EEMWE PORTA2 DDA2 PINA2 PORTB2 DDB2 PINB2
EEAR1 EEWE PORTA1 DDA1 PINA1 PORTB1 DDB1 PINB1
EEAR0 EERE PORTA0 DDA0 PINA0 PORTB0 DDB0 PINB0
19 20 20
EEPROM Data Register (8-Bit)
Universal Serial Interface Data Register (8-Bit) USISIF USISIE USIOIF USIOIE USIPF USIWM1 USIDC USIWM0 USICNT3 USICS1 USICNT2 USICS0 USICNT1 USICLK USICNT0 USITC
83 83 84
ACD REFS1 ADEN
ACBG REFS0 ADSC
ACO ADLAR ADFR
ACI MUX4 ADIF
ACIE MUX3 ADIE
ACME MUX2 ADPS2
ACIS1 MUX1 ADPS1
ACIS0 MUX0 ADPS0
93 103 105 106 106
ADC Data Register High Byte ADC Data Register Low Byte
8
ATtiny26(L)
1477J-AVR-06/07
ATtiny26(L)
Instruction Set Summary
Mnemonic
ADD ADC ADIW SUB SUBI SBC SBCI SBIW AND ANDI OR ORI EOR COM NEG SBR CBR INC DEC TST CLR SER RJMP IJMP RCALL ICALL RET RETI CPSE CP CPC CPI SBRC SBRS SBIC SBIS BRBS BRBC BREQ BRNE BRCS BRCC BRSH BRLO BRMI BRPL BRGE BRLT BRHS BRHC BRTS BRTC BRVS BRVC BRIE BRID MOV LDI LD LD LD Rd, Rr Rd, Rr Rd, Rr Rd, K Rr, b Rr, b P, b P, b s, k s, k k k k k k k k k k k k k k k k k k k Rd, Rr Rd, K Rd, X Rd, X+ Rd, -X k
Operands
Rd, Rr Rd, Rr Rdl, K Rd, Rr Rd, K Rd, Rr Rd, K Rdl, K Rd, Rr Rd, K Rd, Rr Rd, K Rd, Rr Rd Rd Rd, K Rd, K Rd Rd Rd Rd Rd k
Description
Add Two Registers Add with Carry Two Registers Add Immediate to Word Subtract Two Registers Subtract Constant from Register Subtract with Carry Two Registers Subtract with Carry Constant from Reg. Subtract Immediate from Word Logical AND Registers Logical AND Register and Constant Logical OR Registers Logical OR Register and Constant Exclusive OR Registers One's Complement Two's Complement Set Bit(s) in Register Clear Bit(s) in Register Increment Decrement Test for Zero or Minus Clear Register Set Register Relative Jump Indirect Jump to (Z) Relative Subroutine Call Indirect Call to (Z) Subroutine Return Interrupt Return Compare, Skip if Equal Compare Compare with Carry Compare Register with Immediate Skip if Bit in Register Cleared Skip if Bit in Register is Set Skip if Bit in I/O Register Cleared Skip if Bit in I/O Register is Set Branch if Status Flag Set Branch if Status Flag Cleared Branch if Equal Branch if Not Equal Branch if Carry Set Branch if Carry Cleared Branch if Same or Higher Branch if Lower Branch if Minus Branch if Plus Branch if Greater or Equal, Signed Branch if Less than Zero, Signed Branch if Half-carry Flag Set Branch if Half-carry Flag Cleared Branch if T-flag Set Branch if T-flag Cleared Branch if Overflow Flag is Set Branch if Overflow Flag is Cleared Branch if Interrupt Enabled Branch if Interrupt Disabled Move between Registers Load Immediate Load Indirect Load Indirect and Post-inc. Load Indirect and Pre-dec.
Operation
Rd Rd + Rr Rd Rd + Rr + C Rdh:Rdl Rdh:Rdl + K Rd Rd - Rr Rd Rd - K Rd Rd - Rr - C Rd Rd - K - C Rdh:Rdl Rdh:Rdl - K Rd Rd * Rr Rd Rd * K Rd Rd v Rr Rd Rd v K Rd Rd Rr Rd $FF - Rd Rd $00 - Rd Rd Rd v K Rd Rd * ($FF - K) Rd Rd + 1 Rd Rd - 1 Rd Rd * Rd Rd Rd Rd Rd $FF PC PC + k + 1 PC Z PC PC + k + 1 PC Z PC STACK PC STACK if (Rd = Rr) PC PC + 2 or 3 Rd - Rr Rd - Rr - C Rd - K if (Rr(b) = 0) PC PC + 2 or 3 if (Rr(b) = 1) PC PC + 2 or 3 if (P(b) = 0) PC PC + 2 or 3 if (P(b) = 1) PC PC + 2 or 3 if (SREG(s) = 1) then PC PC + k + 1 if (SREG(s) = 0) then PC PC + k + 1 if (Z = 1) then PC PC + k + 1 if (Z = 0) then PC PC + k + 1 if (C = 1) then PC PC + k + 1 if (C = 0) then PC PC + k + 1 if (C = 0) then PC PC + k + 1 if (C = 1) then PC PC + k + 1 if (N = 1) then PC PC + k + 1 if (N = 0) then PC PC + k + 1 if (N V = 0) then PC PC + k + 1 if (N V = 1) then PC PC + k + 1 if (H = 1) then PC PC + k + 1 if (H = 0) then PC PC + k + 1 if (T = 1) then PC PC + k + 1 if (T = 0) then PC PC + k + 1 if (V = 1) then PC PC + k + 1 if (V = 0) then PC PC + k + 1 if (I = 1) then PC PC + k + 1 if (I = 0) then PC PC + k + 1 Rd Rr Rd K Rd (X) Rd (X), X X + 1 X X - 1, Rd (X)
Flags
Z,C,N,V,H Z,C,N,V,H Z,C,N,V,S Z,C,N,V,H Z,C,N,V,H Z,C,N,V,H Z,C,N,V,H Z,C,N,V,S Z,N,V Z,N,V Z,N,V Z,N,V Z,N,V Z,C,N,V Z,C,N,V,H Z,N,V Z,N,V Z,N,V Z,N,V Z,N,V Z,N,V None None None None None None I None Z,N,V,C,H Z,N,V,C,H Z,N,V,C,H None None None None None None None None None None None None None None None None None None None None None None None None None None None None None
# Clocks
1 1 2 1 1 1 1 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 3 3 4 4 1/2/3 1 1 1 1/2/3 1/2/3 1/2/3 1/2/3 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1 1 2 2 2
ARITHMETIC AND LOGIC INSTRUCTIONS
BRANCH INSTRUCTIONS
DATA TRANSFER INSTRUCTIONS
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1477J-AVR-06/07
Instruction Set Summary (Continued)
Mnemonic
LD LD LD LDD LD LD LD LDD LDS ST ST ST ST ST ST STD ST ST ST STD STS LPM LPM IN OUT PUSH POP SBI CBI LSL LSR ROL ROR ASR SWAP BSET BCLR BST BLD SEC CLC SEN CLN SEZ CLZ SEI CLI SES CLS SEV CLV SET CLT SEH CLH NOP SLEEP WDR Rd, Z Rd, P P, Rr Rr Rd P, b P, b Rd Rd Rd Rd Rd Rd s s Rr, b Rd, b
Operands
Rd, Y Rd, Y+ Rd, -Y Rd,Y+q Rd, Z Rd, Z+ Rd, -Z Rd, Z+q Rd, k X, Rr X+, Rr -X, Rr Y, Rr Y+, Rr -Y, Rr Y+q, Rr Z, Rr Z+, Rr -Z, Rr Z+q, Rr k, Rr
Description
Load Indirect Load Indirect and Post-inc. Load Indirect and Pre-dec. Load Indirect with Displacement Load Indirect Load Indirect and Post-inc. Load Indirect and Pre-dec. Load Indirect with Displacement Load Direct from SRAM Store Indirect Store Indirect and Post-inc. Store Indirect and Pre-dec. Store Indirect Store Indirect and Post-inc. Store Indirect and Pre-dec. Store Indirect with Displacement Store Indirect Store Indirect and Post-inc. Store Indirect and Pre-dec. Store Indirect with Displacement Store Direct to SRAM Load Program Memory Load Program Memory In Port Out Port Push Register on Stack Pop Register from Stack Set Bit in I/O Register Clear Bit in I/O Register Logical Shift Left Logical Shift Right Rotate Left through Carry Rotate Right through Carry Arithmetic Shift Right Swap Nibbles Flag Set Flag Clear Bit Store from Register to T Bit Load from T to Register Set Carry Clear Carry Set Negative Flag Clear Negative Flag Set Zero Flag Clear Zero Flag Global Interrupt Enable Global Interrupt Disable Set Signed Test Flag Clear Signed Test Flag Set Two's Complement Overflow Clear Two's Complement Overflow Set T in SREG Clear T in SREG Set Half-carry Flag in SREG Clear Half-carry Flag in SREG No Operation Sleep Watchdog Reset
Operation
Rd (Y) Rd (Y), Y Y + 1 Y Y - 1, Rd (Y) Rd (Y + q) Rd (Z) Rd (Z), Z Z + 1 Z Z - 1, Rd (Z) Rd (Z + q) Rd (k) (X) Rr (X) Rr, X X + 1 X X - 1, (X) Rr (Y) Rr (Y) Rr, Y Y + 1 Y Y - 1, (Y) Rr (Y + q) Rr (Z) Rr (Z) Rr, Z Z + 1 Z Z - 1, (Z) Rr (Z + q) Rr (k) Rr R0 (Z) Rd (Z) Rd P P Rr STACK Rr Rd STACK I/O(P,b) 1 I/O(P,b) 0 Rd(n+1) Rd(n), Rd(0) 0 Rd(n) Rd(n+1), Rd(7) 0 Rd(0) C, Rd(n+1) Rd(n), C Rd(7) Rd(7) C, Rd(n) Rd(n+1), C Rd(0) Rd(n) Rd(n+1), n = 0..6 Rd(3..0) Rd(7..4), Rd(7..4) Rd(3..0) SREG(s) 1 SREG(s) 0 T Rr(b) Rd(b) T C1 C0 N1 N0 Z1 Z0 I1 I0 S1 S0 V1 V0 T1 T0 H1 H0 (see specific descr. for Sleep function) (see specific descr. for WDR/timer)
Flags
None None None None None None None None None None None None None None None None None None None None None None None None None None None None None Z,C,N,V Z,C,N,V Z,C,N,V Z,C,N,V Z,C,N,V None SREG(s) SREG(s) T None C C N N Z Z I I S S V V T T H H None None None
# Clocks
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 3 3 1 1 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
BIT AND BIT-TEST INSTRUCTIONS
10
ATtiny26(L)
1477J-AVR-06/07
ATtiny26(L)
Ordering Information
Speed (MHz) Power Supply Ordering Code ATtiny26L-8PC ATtiny26L-8SC ATtiny26L-8MC 8 2.7 - 5.5V ATtiny26L-8PI ATtiny26L-8SI ATtiny26L-8MI ATtiny26L-8PU(2) ATtiny26L-8SU(2) ATtiny26L-8MU(2) ATtiny26-16PC ATtiny26-16SC ATtiny26-16MC 16 4.5 - 5.5V ATtiny26-16PI ATtiny26-16SI ATtiny26-16MI ATtiny26-16PU(2) ATtiny26-16SU(2) ATtiny26-16MU(2)
Package(1)
Operational Range Commercial (0C to 70C)
20P3 20S 32M1-A 20P3 20S 32M1-A 20P3 20S 32M1-A 20P3 20S 32M1-A 20P3 20S 32M1-A 20P3 20S 32M1-A
Industrial (-40C to 85C)
Commercial (0C to 70C)
Industrial (-40C to 85C)
Notes:
1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and minimum quantities. 2. Pb-free packaging alternative, complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also Halide free and fully Green.
Package Type 20P3 20S 32M1-A 20-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP) 20-lead, 0.300" Wide, Plastic Gull Wing Small Outline (SOIC) 32-pad, 5 x 5 x 1.0 body, Lead Pitch 0.50 mm Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF)
11
1477J-AVR-06/07
Packaging Information
20P3
D
PIN 1
E1
A
SEATING PLANE
L B1 e E B
A1
C eC eB
SYMBOL A A1 D E E1 B Notes: 1. This package conforms to JEDEC reference MS-001, Variation AD. 2. Dimensions D and E1 do not include mold Flash or Protrusion. Mold Flash or Protrusion shall not exceed 0.25 mm (0.010"). B1 L C eB eC e
COMMON DIMENSIONS (Unit of Measure = mm) MIN - 0.381 25.493 7.620 6.096 0.356 1.270 2.921 0.203 - 0.000 NOM - - - - - - - - - - - MAX 5.334 - 25.984 8.255 7.112 0.559 1.551 3.810 0.356 10.922 1.524 Note 2 Note 2 NOTE
2.540 TYP
1/12/04 2325 Orchard Parkway San Jose, CA 95131 TITLE 20P3, 20-lead (0.300"/7.62 mm Wide) Plastic Dual Inline Package (PDIP) DRAWING NO. 20P3 REV. C
R
12
ATtiny26(L)
1477J-AVR-06/07
ATtiny26(L)
20S
13
1477J-AVR-06/07
32M1-A
D D1
1 2 3
0
Pin 1 ID E1 E
SIDE VIEW
TOP VIEW
A2
A3 A1
K
P D2
A
0.08 C
COMMON DIMENSIONS (Unit of Measure = mm) MIN 0.80 - - NOM 0.90 0.02 0.65 0.20 REF 0.18 4.90 4.70 2.95 4.90 4.70 2.95 0.23 5.00 4.75 3.10 5.00 4.75 3.10 0.50 BSC 0.30 - - 0.20 - 0.40 - - 0.50 0.60 12o - 0.30 5.10 4.80 3.25 5.10 4.80 3.25 MAX 1.00 0.05 1.00 NOTE
SYMBOL A
P
Pin #1 Notch (0.20 R)
1 2 3
A1 A2 A3 E2 b
K
D D1 D2 E
b
e
L
E1 E2 e L P
BOTTOM VIEW
0
Note: JEDEC Standard MO-220, Fig. 2 (Anvil Singulation), VHHD-2. K
5/25/06 2325 Orchard Parkway San Jose, CA 95131 TITLE 32M1-A, 32-pad, 5 x 5 x 1.0 mm Body, Lead Pitch 0.50 mm, 3.10 mm Exposed Pad, Micro Lead Frame Package (MLF) DRAWING NO. 32M1-A REV. E
R
14
ATtiny26(L)
1477J-AVR-06/07
ATtiny26(L)
Errata
ATtiny26 Rev. B/C/D
The revision letter refers to the revision of the device. * First Analog Comparator conversion may be delayed 1. First Analog Comparator conversion may be delayed If the device is powered by a slow rising VCC, the first Analog Comparator conversion will take longer than expected on some devices. Problem Fix/Workaround When the device has been powered or reset, disable then enable the Analog Comparator before the first conversion.
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1477J-AVR-06/07
Datasheet Revision History
Rev. 1477J-06/07 Rev. 1477I-10/06 Rev. 1477H-04/06
Please note that the referring page numbers in this section are referred to this document. The referring revision in this section are referring to the document revision. 1. "Not recommended for new design" 1. Updated "Errata" on page 15 1. Updated typos. 2. Added "Resources" on page 6. 3. Updated features in "System Control and Reset" on page 33. 4. Updated "Prescaling and Conversion Timing" on page 98. 5. Updated algorithm for "Enter Programming Mode" on page 114.
Rev. 1477G-03/05
1. MLF-package alternative changed to "Quad Flat No-Lead/Micro Lead Frame Package QFN/MLF". 2. Updated "Electrical Characteristics" on page 128 3. Updated "Ordering Information" on page 11
Rev. 1477F-12/04
1. Updated Table 16 on page 34, Table 9 on page 29, and Table 29 on page 59. 2. Added Table 20 on page 41. 3. Added "Changing Channel or Reference Selection" on page 100. 4. Updated "Offset Compensation Schemes" on page 107. 5. Updated "Electrical Characteristics" on page 128. 6. Updated package information for "20P3" on page 12. 7. Rearranged some sections in the datasheet.
Rev. 1477E-10/03
1. Removed Preliminary references. 2. Updated "Features" on page 1. 3. Removed SSOP package reference from "Pin Configuration" on page 2. 4. Updated VRST and tRST in Table 16 on page 34. 5. Updated "Calibrated Internal RC Oscillator" on page 30. 6. Updated DC Characteristics for VOL, IIL, IIH, ICC Power Down and VACIO in "Electrical Characteristics" on page 128.
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7. Updated VINT, INL and Gain Error in "ADC Characteristics" on page 131 and page 132. Fixed typo in "Absolute Accuracy" on page 132. 8. Added Figure 106 in "Pin Driver Strength" on page 148, Figure 120, Figure 121 and Figure 122 in "BOD Thresholds and Analog Comparator Offset" on page 157. Updated Figure 117 and Figure 118. 9. Removed LPM Rd, Z+ from "Instruction Set Summary" on page 9. This instruction is not supported in ATtiny26.
Rev. 1477D-05/03
1. Updated "Packaging Information" on page 12. 2. Removed ADHSM from "ADC Characteristics" on page 131. 3. Added section "EEPROM Write During Power-down Sleep Mode" on page 21. 4. Added section "Default Clock Source" on page 27. 5. Corrected PLL Lock value in the "Bit 0 - PLOCK: PLL Lock Detector" on page 76. 6. Added information about conversion time when selecting differential channels on page 99. 7. Corrected {DDxn, PORTxn} value on page 45. 8. Added section "Unconnected Pins" on page 48. 9. Added note for RSTDISBL Fuse in Table 50 on page 110. 10. Corrected DATA value in Figure 61 on page 118. 11. Added WD_FUSE period in Table 60 on page 125. 12. Updated "ADC Characteristics" on page 131 and added Table 66, "ADC Characteristics, Differential Channels, TA = -40C to 85C," on page 132. 13. Updated "ATtiny26 Typical Characteristics" on page 133. 14. Added LPM Rd, Z and LPM Rd, Z+ in "Instruction Set Summary" on page 9.
Rev. 1477C-09/02 Rev. 1477B-04/02
1. Changed the Endurance on the Flash to 10,000 Write/Erase Cycles. 1. Removed all references to Power Save sleep mode in the section "System Clock and Clock Options" on page 24. 2. Updated the section "Analog to Digital Converter" on page 96 with more details on how to read the conversion result for both differential and singleended conversion. 3. Updated "Ordering Information" on page 11 and added QFN/MLF package information.
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Rev. 1477A-03/02
1. Initial version.
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1477J-AVR-06/07

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